Hardware Evaluation of The Hash Function Hamsi

This document describes ASIC and FPGA implementations of the hash function Hamsi. The results show that Hamsi can be efficiently implemented in hardware with small area. We also point out several optimization methods targeting different design goals. 1 Design Guideline The current implementations are straightforward realizations of the Hamsi hash function family. In other words, higher throughput or lower footprint should be achievable by applying certain optimization methods. 2 Architecture The hash function Hamsi is based on a message expansion function and iterated transformations. Let Mi and iv denote a message block and the initial value, respectively, then the hash value h is computed as follows: hi = (T ◦ P ◦ C(E(Mi), hi−1))⊕ hi−1, h0 = iv, 0 < i < l (1) h = (T ◦ Pf ◦ C(E(Ml), hl−1))⊕ hl−1 (2) Here E,C, P, T denote Message Expansion, Concatenation, Non-linear Permutation and Truncation, respectively. Non-linear Permutation P (Pf for the last message block) consists of three layers, namely, addition of constants and a counter, substitution and diffusion layer. Pf differs from P in only constants and the number of rounds. The complete description of Hamsi can be obtained from the specification [4]. Figure 1 shows the architecture of the Hamsi coprocessor. The coprocessor consists of a main controller, combinational logic for E,C, P, T , and three registers. The last message block is also hashed with the same circuit, while it use different constant and more rounds are applied. Note that we assume that message padding is performed by the main CPU, the Hamsi coprocessor reads the message from a shared memory. The results is in the cvalue register and shifted out word-by-word. Message Expansion Concatenation